This invention relates generally to complementary metal-oxide-semiconductor (CMOS) integrated circuits and more particularly, it relates to balanced CMOS logic circuits which are arranged on an integrated circuit substrate with topological regularity.
Heretofore, conventional CMOS circuits have been laid out on integrated substrates in a random topological manner which occupies a considerable amount of space area on the substrate. Due to this random layout, the architecture of the prior art circuits require an increased number of interconnecting leads between the various individual circuit elements as well as a high number of power leads which run in an inefficient manner throughout the circuits. As a consequence, the prior art conventional CMOS suffered from the disadvantages of slower speed of operation and high manufacturing cost.
It would therefore be desirable to provide balanced CMOS logic circuits which are arranged on an integrated circuit substrate with topological regularity so as to require a lesser amount of integrated surface area. By utilizing an integrated circuit with reduced surface area, the implementation of various logic circuits on the substrate will minimize the operating load routing requirements which will improve the speed and efficiency of operation of the circuit.
As used herein, "topological regularity" refers to a layout conforming to a repeatable pattern suitable for high-density large scale integration (LSI). As should be apparent to those skilled in the art, custom designed logic circuit chips for LSI are expensive and require high usage for justification. Thus, it would be more expedient to design a particular type of logic circuit which could be used as a standard module. Then, the standard module would be layed out repeatedly on the integrated circuit substrate so as to yield high packing density without increasing the size disproportionately.